The use of digital video signals to represent video data is becoming commonplace. Various encoding and data compression methods have been proposed for the encoding and transmission of video signals.
The International Organization for Standardization has set a standard for video data compression for generating a compressed digital data stream that is expected to be used for digital television. This standard is referred to as the ISO MPEG standard (International Organization for Standardization--Moving Picture Experts Group) or simply the MPEG standard.
One version of the MPEG standard, MPEG-2, is described in the International Standards Organization--Moving Picture Experts Group, Drafts of Recommendation H.262, ISO/IEC 13818-1 and 13818-2 titled "Information Technology--Generic Coding of Moving Pictures and Associated Audio". The MPEG-2 standard provides a large amount of discretion with regard to encoding practices and to a large extent serves primarily to define what capabilities a reference decoder must have to decode a stream of MPEG video data.
Recommendations for the encoding of video and audio information in accordance with the MPEG standard are set forth in a document referred to as Test Model 5, ISO-IEC/JTC1/SC29/WG11 Coded Representation of Picture and Audio Information dated April 1993 (hereinafter "the MPEG-2 Test Model").
The MPEG standard as well as other digital encoding methods allow video images to be represented using different amounts of data. Generally, the more data used to represent a video image, e.g., frame, the more faithful the representation of the image. For example, a frame of video may be encoded, in accordance with MPEG-2 as high definition (HD), or standard definition (SD) video signals. In this application HD is used to refer to video signals or images having a higher degree of resolution than standard analog NTSC video images while SD is used to refer to video signals or images having approximately the same resolution as standard analog NTSC video images.
Generally, it has been the practice to encode and decode video data using encoders and decoders which are matched to the degree of resolution used to represent the video images. For example, as illustrated in FIG. 1A a HD video decoder is normally used to decode HD bitstream generated by a HD encoder 12. Similarly, a SD video decoder 18 is normally used to decode a SD video bitstream such as the SD bitstream generated by the SD Encoder 16 illustrated in FIG. 1B. By using a decoder matched to the encoder, the encoded bitstream is normally decoded at or near the full resolution at which is encoded.
Because of the higher memory requirements and the general complexity of an HD decoder, HD decoders generally cost more to implement than SD decoders. In the area of low cost electronics, e.g., low end consumer electronics, cost is a major factor in determining a products success in the market place. In order to reduce the cost of a high definition decoder, various techniques may be used to reduce the data rate and/or resolution of the video frames in an encoded bitstream and/or the amount of processing that must be performed as part of the decoding process. Such data reduction and video processing techniques, e.g., downsampling, will be referred to generally as downconverting. Downconverting generally results in lower quality, e.g., lower resolution video images being generated than would result if the encoded bitstream were decoded without downconverting. Decoders which perform downconverting as part of the decoding process are referred to as downconverting decoders.
When a high resolution, e.g., HDTV, bitstream is downconverted, the resulting image quality is dependent on choices made by the original encoder, e.g., the HD encoder at encoding time.
Referring now to FIG. 2, there is illustrated a known encoder 20 for encoding video signals as, e.g., HD video signals.
The known encoder 20 includes a summer 26, a compression circuit 27, a variable length coding (VLC) circuit 28 and a decompression circuit 29. As illustrated, a summing input of the summer 26 receives the input video signal. A video feedback signal which is provided by the decompression circuit 29 is subtracted from the input signal by the summer 26 to produce the video prediction error signal which is supplied to an input of the compression circuit 27. The compression circuit performs data compression, e.g., by performing discrete cosine transform (DCT), coding and quantization, on the video bitstream.
The compressed video bitstream output by the compression circuit 27 is supplied to an input of the VLC circuit 28 and the decompression circuit 29. The decompression circuit 29 decompresses the compressed video bitstream to generate the feedback signal supplied to the summer 26. The feedback signal is used to facilitate the data compression operation performed by the compression circuit 27 and to minimize artifacts therefrom. The VLC circuit variable length encodes the compressed video bitstream output by the compression circuit 27 and supplies a feedback signal to the compression circuit for controlling the quantization rate and thus the amount of data compression to insure, e.g., that the bitrate output by the VLC circuit is maintained within the desired bounds.
Referring now briefly to FIG. 3, the known encoder circuit 20 is illustrated in greater detail. As illustrated in FIG. 3, the compression circuit of the known decoder includes a discrete cosine transform (DCT) circuit 330 which receives the video bitstream to be compressed and performs discrete cosine transform coding operations thereon. The output of the DCT circuit 330 is coupled to the input of a quantization circuit 332. The quantization circuit 332 receives as a control signal an input from an MQUANT selection circuit 334 where the value MQUANT is used to control the quantization scale factor used during quantization. The MQUANT selection circuit 334 is coupled to an output of the VLC circuit 28 and is responsible for selecting a quantization scale factor which will achieve the desired data rate as a function of the feedback information obtained from the VLC circuit 28. The quantized video signal output by the quantization circuit 332 is the compressed video signal that is supplied to the input of the VLC circuit 28 and the decompression circuit 29.
The decompression circuit 29 comprises an inverse quantization circuit 340 coupled to an inverse discrete cosine transform (IDCT) circuit 341. As is known in the art the output of the IDCT circuit 341 is coupled to a first summing input of a summer 342. A second input of the summer 342 is coupled to the output of a motion compensation circuit 344. The output of the summer 342 is coupled to an input of an anchor frame storage unit 343 which has a first output coupled to an input of a motion estimation circuit 345. A second output of the anchor frame storage unit 343 is coupled to a first input of the motion compensation circuit 344 while a second input of the motion compensation circuit 344 is coupled to an output of the motion estimation circuit 345. The output of the motion compensation circuit 344 represents a predicted picture which is used as a feedback signal to the summer 342 and the summer 26. The various elements of the decompression circuit 29 work together as is known in the art, to decompress the compressed video bitstream output by the compression circuit 27 and to provide a feedback video signal, which, in the case of video data that is being inter-coded, is selectively subtracted from the input video signal by the summer 26 as is known in the art.
While the known encoder circuit 20 provides feedback from the VLC circuit to control the output bit rate and includes a decompression circuit which provides feedback relating to the full decoding of the compressed video bitstream, the known encoder fails to include circuitry to take into consideration the effect that downconverting will have on the video data being encoded or the effect that various downconverting decoder processing or data storage limitations may have on the ability to decode the video bitstream generated by the known encoder. For example, the known decoder circuit 20 fails to take into account the effect of discarding high frequency DCT coefficients and/or downsampling the encoded video data will have on downconverted image quality.
In order to enhance the quality of video images generated by a downconverting decoder, there is a need for encoder methods and apparatus which can produce a high resolution, e.g., a HD, bitstream which is well suited for decoding by both a downconverting decoder as well as a high resolution decoder.
Furthermore, it is desirable that an encoder be capable of taking into account the effect of various anticipated downconverting operations, e.g., downsampling, will have on the quality of encoded video that is decoded by a downconverting video decoder. It is also desirable that an encoder be capable of taking into consideration data processing limitations, e.g., buffer size limitations, that may exist in downconverting decoders that are expected to be used to decode the video bitstream generated by the encoder.